Field Effect Transistor (FET) devices are widely used in microelectronic fabrication of Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices, and in microwave and other radio frequency devices. FET's have long been implemented using silicon semiconductor technology in the form of Metal Oxide Semiconductor Field Effect Transistors (MOSFET), also referred to as Metal Insulator Field Effect Transistors (MISFET) or Insulated Gate Field Effect Transistors (IGFET). There has also been some activity in implementing FETs in germanium and other single element semiconductors.
Recently much interest has developed in compound semiconductor materials such as gallium arsenide (GaAs) and indium phosphide (InP). Such compound semiconductors have been widely investigated for VLSI and ULSI devices, for high frequency (millimeter or microwave) devices and for lasers. Compound semiconductor materials have a higher electron mobility and electron velocity than single element semiconductors, as well as a higher insensitivity to radiation.
As is well known to those having skill in the art a FET comprises source and drain regions formed in one face of a semiconductor substrate and a channel formed in the semiconductor substrate between the source and drain regions. Source, drain and gate contacts are provided for the source, drain and channel respectively. In compound semiconductor FET devices an insulator, often in the form of an oxide, may be included between the channel and the gate contact to mimic the MISFET structure of single element semiconductor devices. See for example Japanese published patent application 61-60519 to Sakamoto, published Sept. 26, 1987 which discloses a gallium arsenide MISFET having a large threshold voltage, and including a gate electrode on a semi-insulating gallium arsenide film which overlies the channel, in which the gallium arsenide semi-insulating film may be formed by molecular beam epitaxy or molecular chemical vapor deposition. See also U.S. Pat. No. 4,450,462 to Nuyen which discloses a MISFET formed in gallium arsenide.
Much investigation has also been directed to unique FET structures for compound semiconductor devices. In particular, a class of devices often called MEtal Semiconductor Field Effect Transistors (MESFET) includes a gate contact which lies directly on the channel, without an intervening oxide or insulating layer. MESFETs operate under principles of geometry control with the gate voltage controlling the channel geometry. Efforts have also been made to improve the performance of compound semiconductor FETs by providing heterostructures within the devices to form a High Electron Mobility (HEMT) field effect transistor, also referred to as a MOdulation Doped FET (MODFET). In the HEMT, a two-dimensional electron gas is created in the heterostructure, with charge control mechanisms operating to control the electron gas.
Voltage breakdown has long been a limiting factor in FET devices. Breakdown is the well known phenomena in which application of a voltage greater than the breakdown voltage causes avalanche multiplication of carriers in the device. Gate breakdown has been experienced in silicon-based FET technology, wherein logic voltages of five volts or more must be withstood by the gate. However, the presence of an oxide or insulator region between the gate electrode and the channel tends to increase gate breakdown, and an oxide between the gate and drain tends to increase the transconductance and adversely effect device performance.
Gate breakdown has been the most limiting factor in compound semiconductor FETs, and in particular in MESFETs and HEMTs wherein a gate insulator is not used. In particular, the major drawback of the MESFET/HEMT in microwave applications has been its efficiency as a high power source. The limit to both its output power and efficiency is the breakdown voltage of the gate. This problem is very important at "C" and "X" band frequencies and becomes crucial at millimeter wave frequencies. Often, breakdown voltages of less than five volts under open channel current conditions are observed, thereby greatly decreasing the usefulness of these devices. To compensate for this breakdown, multiple devices must often be used instead of a single device in order to allow high power output without breakdown.
Since gate breakdown is the limiting factor in compound semiconductor MESFETs and HEMTs, many attempts have been made to produce these FETs with high gate breakdown voltage. For example, many techniques have attempted to increase the breakdown voltage of the FET by limiting the current which can be handled thereby. Unfortunately this current versus voltage tradeoff does not increase the overall power which can be handled by the FET. One example of this technique may be found in published European patent application 186,058, published July 19, 1986, which describes a lightly doped drain (LDD) FET in which the drain side of the channel has a lighter doping concentration than the source side of the channel. Another example of this technique is shown in U.S. Pat. No. 4,656,492 to Sunami et al., in which the doping distribution in the channel is gently sloped, to limit the channel current and avoid breakdown.
Other techniques for increasing the breakdown voltage of MESFETs and HEMTs require physical shaping of the channel to prevent breakdown. Unfortunately, these techniques also involve a tradeoff between current capacity and voltage breakdown so that greater overall power handling ability does not result. Moreover, channel shaping requires complex processing steps. See for example published Japanese patent application 62-19897 to Saito, published on Aug. 3, 1988, which discloses a high breakdown voltage gallium arsenide FET having an active layer which is thicker between the gate and source than between the gate and drain. A similar physical shaping technique is disclosed in an article entitled "Improvement of the Drain Breakdown Voltage of GaAs Power MESFETs By A Simple Recess Structure" published in the IEEE Transactions on Electron Devices, Volume ED-25 No. 6, June 1978, pages 563-567 to Furutsuka et al. Disclosed is a recess structure which improves breakdown voltage by increasing the thickness of the active epitaxial layer at the drain contact region.
Other techniques have been employed to prevent electrons from being captured by the gate electrode during breakdown. See for example Japanese published patent application 62-99898 to Kimura, published Nov. 2, 1988. Disclosed is a MISFET having a polysilicon layer within the gate insulating layer. This polysilicon layer captures electrons or holes produced. However this layer will not prevent breakdown between the gate and drain or the gate and source; it merely prevents electrons from being captured in the gate contact during breakdown.
A theoretical study of the breakdown physics of a gallium arsenide MESFET was published in Solid State Electronics, Volume 29, No. 8, pages 807-813, 1986 under the title "The Role of the Device Surface in the High Voltage Behavior of the GaAs MESFET", by Barton et al. Barton et al. discloses that surface effects can have a large impact in determining GaAs MESFET characteristics at high voltages. In particular, it was shown in this study that the large electric field that forms at the drain end of the gate in a MESFET, and that is primarily responsible for breakdown occurring at the gate edge, is caused by excess surface charge. Although this theoretical study investigated breakdown models for FETs, no techniques were disclosed to increase breakdown voltage of the FET.